FPGA Engineer
Family: Low-level & domain-heavy
Programs field-programmable gate arrays to implement hardware-accelerated logic for networking, signal processing, and HPC workloads.
Day to day
Authors RTL designs in VHDL or Verilog, synthesizes and places bitstreams, writes HLS kernels, and verifies timing closure and correctness through simulation and hardware testing.
Core skills
- VHDL/Verilog
- HLS
- timing analysis
- Vivado/Quartus
- hardware-software co-design