ASIC Engineer
Family: Low-level & domain-heavy
Designs custom silicon — from RTL through physical implementation — to meet performance and power targets no general-purpose chip can match.
Day to day
Writes RTL in SystemVerilog or VHDL, runs synthesis and timing analysis, works with physical design teams on floorplanning, and closes timing across process corners.
Core skills
- SystemVerilog
- RTL design
- synthesis
- timing closure
- VLSI