Hardware Verification Engineer
Family: Low-level & domain-heavy
Verifies that hardware designs are functionally correct before tape-out using simulation, formal methods, and coverage-driven verification.
Day to day
Writes UVM testbenches, develops functional coverage models, runs regression suites, triages simulation failures, and works with design engineers to close coverage goals.
Core skills
- SystemVerilog
- UVM
- functional coverage
- formal verification
- simulation